The following European Patent application numbers are cross-referenced:
European patent application no. 97480057.5 filed on Aug. 19, 1997 entitled xe2x80x9cSwitching System Comprising Distributed Elements Allowing Attachment to Line Adapters, and Having Multicasting Capabilitiesxe2x80x9d describes the detail of the techniques used for building large Switching architectures with sophisticated SCAL elements.
European application no. 97480056.7.
European application no. 97480065.8.
European application no. 96480129.4.
European application no. 96480120.3.
European application no. 98480039.1, filed on May 29, 1998 and entitled xe2x80x9cSwitching Architecture Comprising Two Switch Fabricsxe2x80x9d.
European Application no. 97480100.3, from A. Blanc et al., filed on Dec. 30, 1997, and entitled xe2x80x9cPort Expansion Architecture for Large Cell Switchxe2x80x9d.
European Application no. 97480098.9, from A. Blanc et al., filed on Dec. 30, 1997, and entitled xe2x80x9cProcess for Transporting and Routing a Cell in a Switching Structure Based on a Single Storage Switchxe2x80x9d.
European Application no. 97480101.1, from A. Blanc et al., filed on Dec. 30, 1997, and entitled xe2x80x9cCongestion Management in Very Large Switching Fabricsxe2x80x9d.
European Application no. 97480099.7, from A. Blanc et al., filed on Dec. 30, 1997, and entitled xe2x80x9cOptional Back Pressure in ATM Switching Fabricxe2x80x9d.
European Application no. 98480007.8, from A. Blanc et al., filed on Feb. 19, 1998, and entitled xe2x80x9cFlow Control Process for a Switching System, and System for Performing the Samexe2x80x9d.
European Application no. 98480006.0, from A. Blanc et al., filed on Feb. 19, 1998, and entitled xe2x80x9cFlow Control Process for a Switching Architecture Using an Out-of-Band Flow Control Channel, and Apparatus for Performing the Samexe2x80x9d.
European Application no. 98480039.1, from A. Blanc et al., filed on May 29, 1998, and entitled xe2x80x9cSwitching Architecture Comprising Two Switch Fabricsxe2x80x9d discloses a switch-over when a maintenance operation is planned in one component of the active Switch over.
European Application no. 98480040.9, from A. Blanc et al., filed on May 29, 1998, and entitled xe2x80x9cFault Tolerant Switching Architecturexe2x80x9d discloses a second case of switch-over that is arranged when a breakdown condition occurs in one Switch Fabric.
1. Field of the Invention
The invention relates to switching systems and, more particularly, to a Switch Fabric system which comprises at least one Switch Fabric subsystem including a set of Switch core elements being arranged in port expansion architecture.
2. Background Art
Shared buffer switches have been shown to be of great interest for switching small packets of data and well adapted to the switching of Asynchronous Transfer Mode (ATM) cells although they are not limited to the ATM technology. Basically, a shared buffer switch comprises a cell storage which is used for storing the cells which are entering through one input port of the switch. An appropriate mechanism is used for extracting the cell from the shared buffer and for directing the latter to one or more output ports of the switch. By using different output queues, each one dedicated to one output port of the switch, it is made possible to achieve a very simple multicasting effect in the switching process. Additionally, the provision of Switch Core Access Layer (SCAL) elements combined with a centralized switching system, the SCAL being located remote, allows an increasing traffic to be transported through the latter.
The high speed requirements of switching systemsxe2x80x94resulting of a huge amount of these small cells to be switched per periodxe2x80x94tend to force the known technology well beyond its possibilities and physical limits. Special arrangements had to be designed for going beyond the physical limit of the today technology. This was basically achieved by expanding the switching architecture in three directions.
A first way is what is known under the concept of speed expansion which allows an effective combination of several distinctive individual switching modules together; e.g., four modules, in order to form an aggregate high-rate Switching structure or Switch Core. To achieve this, the cell is divided in separate Logical Units (LU) and each one is directed to one switching module. By means of an appropriate mechanism, the four modules can be coupled and synchronized under the control of a master module which permits simultaneous routing of the four LUs towards the same destination port. This obviously permits increasing the overall switching speed, although the semiconductor technology remains unchanged.
These documents disclose the internal control of the different modules by a single master module in accordance with a bit map value introduced in the cell when the latter arrives into the switch core. The particular value that is introduced is extracted from a Routing Control Table that is associated with the master switching module.
In addition to the speed-expansion direction, the port expansion is another direction for an effective combination of individual modules in order to extend, to compensate the physical limitations of a given technology. An example of a port expansion architecture which permits multiplying the number of Port Adapters by two is shown in FIG. 1. A combination of four different Switching Structures or Switch Cores 111, 112, 121 and 122 (each one possibly comprising four switching modules if speed expansion is applied) which are arranged so as to allow the attachment of two sets of Protocol Adapters (PA). Assuming, for instance, that the number of input and output ports is fixed to 16, the port expansion architecture allows a first set of sixteen Protocol Adapters 1-1 to 1-16 and a second set of sixteen Protocol Adapters 2-1 to 2-16 to be connected to the Switch Fabric. More particularly, the input ports i of Switch Cores 111 and 112 are connected together by means of a fan-out circuit 110-i in order to receive the same flow of cells coming from Protocol Adapter 1-i (and, more particularly, the Receive part of the latter). Similarly, Protocol Adapter 2-i produces cells which are transported via the SCAL receive part.
For the sake of clarity, only one port is represented in FIG. 1 which shows that Switch cores 111 and 112 have an input port i that receives the cells coming from the receive part of Protocol Adapter 1-i and transported via SCAL_Receive element 11-i, serial long distance transmission link 13-i and fan-out circuit 110-i. Similarly, Switch cores 121 and 122 has an input port i that receives the cells coming from the receive part of Protocol Adapter 2-i and transported via SCAL_Receive element 21-i, long distance serial transmission link 23-i and fan-out circuit 120-i. 
With respect to the output ports of the switch cores, and particularly for output port j, the figure shows that Switch cores 111 and 121 are connected to the Xmit part of Protocol Adapter 1-j via fan-in circuit 131-j, long distance serial transmission link 13-j and SCAL Xmit element 11-j. Similarly, Switch cores 112 and 122 are connected to the Xmit part of Protocol Adapter 2-j via fan-in circuit 132-j, long distance serial transmission link 23-j and SCAL Xmit element 21-j. Long distance serial transmission links 13-i, 23-i, 13-j and 23-j are optical or cables that are adapted to the transmission of data rates at high speeds so that Protocol Adapters located at different areas, up to several hundreds of meter, can be attached to the centralized port expansion switching architecture. A known communication link can be found in document xe2x80x9cSingle-chip 4xc3x97500 Mbaud CMOS Transceiverxe2x80x9d from A. Widmer et al, in IEEE ISSCC96, Session 7. ATM/SOMET/PAPER FA7.7. Published on Feb. 9, 1996 for providing 1.6 Gigabit/s communication links. When the Switch Core comprises four individual Switching modules arranged in speed expansion, link 13-i comprises a set of four different serial links that are separately assigned to the transport of one dedicated Logical Unit.
In addition to the speed expansion mechanism and the buffer expansion mechanism, an arrangement permits the increase of storage of the shared buffer by combining two different modules in a buffer expansion mechanism.
New requirements of fault tolerance also require the multiplication of the individual modules. This is shown in a fault tolerance architecture of FIG. 2 which shows two basic Switch Fabrics 100 and 200 which each comprise at least one Switch Core (which can also include multiple switching modules in accordance with the number of Logical Units being considered). Each Protocol Adapter, PA 1-i for instance, is attached to both Switch Fabrics 100 and 200 via a SCAL element 11-i and 12-i. Similar to the illustration of FIG. 1, only one port (i) is represented with respect to the input side of the Switch Fabric, and one port j for the output side. By means of an appropriate masking mechanism, the routing process routing may be altered so as to permit the cells, which are normally transported via one Switch Fabric being considered as active, to be routed via the backup Switch Fabric 200.
The following non-published European patent applications disclose a very effective way of permitting a switch-over from one Switch Fabric to the other one when either a maintenance operation is planned or when breakdown conditions occur.
As a conclusion, it appears that the modern switching architectures, cumulating speed expansion, buffer expansion and fault-tolerance capability tend to substantially multiply the number of individual Switching Modules that are to be used in the Switch Core. Therefore, this substantially increases the difficulty to manage the routing process within so many different Switching Structures that are all associated to different Routing Control Tables for the generation of the bit map value when the cell enters one Switch Core. Obviously, each Routing Control table contains different values and must be efficiently updated in accordance with the ongoing establishment and clearance of connections.
It is an object of the present invention to provide a management process of the different Routing Control tables that are used in large Switch fabrics made up of numerous Switch cores arranged in speed expansion, port expansion, buffer expansion as well as in fault tolerance architectures.
It is another object of the present invention to provide a Switching architecture that permits the continuous update of the routing tables that are distributed in the different individual Switch Cores.
It is a further object of the present invention to provide a switching control driver for a large shared-buffer Switch Fabric comprising multiple different Switch cores or Switch cores.
These and other objects of the invention are provided by the Switch Fabric system which is defined in the set of claims. Basically, the Switch Fabric system comprises at least one Switch Fabric subsystem which further includes a set of Switch cores elements being arranged in a port expansion for the attachment of at least a first and second sets of Protocol Adapters. At least one common control bus permits communication between the different Switch Cores. The switching control process is achieved by means of a combination of one Protocol Adapter acting as a Primary Switch Controller (PSC) centralizing the communication between the switch and the upper layer application, and the different Switch Core elements which operate as Secondary Switch Controller (SSC). The Primary Switch controller has a complete knowledge of the topology of the switch; e.g., the number of subsystems, the nature of the port expansion, etc.
One particular Switch Core which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem. Preferably, the Switch Fabric system comprises two Switch Fabric Subsystems that are mounted in fault tolerance arrangement so that each Protocol Adapter may receive cells via two parallel paths.
In a preferred embodiment of the invention, each switch core is associated with at least one Routing Control table which is used for producing a bit map value for controlling the internal routing process into the switch core. Effective communication between the Primary Switch Controller, the focal point Secondary Switch Controller and the other SSCs, permits an easy and effective update process of the different Routing Control tables.
Still preferably, each Protocol Adapter is assigned a particular Unicast routing index which it receives from the attached Switch core during an initialization procedure, the Unicast routing index being different from the routing index of said Primary Switch Controller and said Secondary Switch controllers. Each Protocol Adapter further comprises means for requesting the role of the Primary Switch Controller during the initialization procedure.
In a preferred embodiment of the invention, the Primary Switch Controller which has received its Unicast routing index from the Switch Core to which it is attached then transmits a particular cell having a predefined routing index to said Switch Core, so as to inform the latter that it has full-duplex communication capability with the Primary Switch Controller and that it will be used as a focal point for the other Secondary Switch Controllers in the same Subsystem.